The present disclosure relates to an interconnect for connecting conductive portions in electronic components, and in particular to, interconnects of one or more carbon nanofiber structures to connect conductive portions in the electronic components.
As pitch sizes of electronic devices have decreased, techniques involved in the development of such devices have also evolved in order to maintain their performance capability. However, with this increased performance, additional constraints on the electric power and thermal distribution of the semiconductor device have been discovered. As the system performance of a device increases, the density of the interconnect feature also increases, and, as a result, each interconnect feature is limited to usage at specific technology nodes in one particular semiconductor material.
More specifically, different device technologies may be associated with different connective properties which constrain the techniques which can be used in additive processing. For example, the connectivity of GaN devices to silicon technologies has thermal limits to incorporating one layer. GaN layers are generally deposited around a temperature of 1000° C., whereas silicon technologies often have a thermal limitation of approximately 400° C. As a result, conventionally, the two materials must be formed separately and joined together to form the final interconnect feature.
However, as the pitch, or size, of an interconnect feature decreases, conventional techniques are no longer as effective. For smaller interconnect features, adjoining materials requires a greater capacity for thermal expansion, which means with lower interconnect temperatures, additional bonding may be required for materials with lower bonding temperatures, further complicating the design process. Moreover, interconnect features of smaller pitch sizes will have different electrical characteristics than the same bulk material, for example a higher electrical resistance due to the reduced geometry of the material which causes a decrease in the electrical performance of the interconnect, for example the current carrying capacity. As a result, there exists a need for a technique for designing small interconnect features which accounts for technical considerations, such as thermal limitations and increased resistance readings.